The present invention relates to techniques for implementing hardwired decoders in differential input circuits, and more particularly, to techniques for decoding differential input signals using hardwired decoders in two adjacent rows/columns of programmable logic elements on a programmable integrated circuit.
Altera Corporation of San Jose, Calif. is a manufacturer of field programmable gate array (FPGA) devices. Stratix® I FPGAs and Stratix II FPGAs are two high end FPGA devices made by Altera. Stratix I FPGAs and Stratix II FPGAs contain hardwired (hard) serializer-deserializer (SERDES) and hard double data rate input/output (DDIO) blocks that target high system interface performance.
Hard SERDES and hard DDIO blocks provide better timing skew and specifications compared to soft SERDES and soft DDIO blocks. The term “soft” refers to building these blocks with programmable logic circuits. Hard DDIO and SERDES blocks also have the advantage of having a larger receiver input skew margin.
Hard SERDES and hard DDIO have not be added to the architecture of Altera's low cost Cyclone™ FPGA in order to save die area. Therefore, core programmable logic circuits and programmable interconnect wires are used to build the soft SERDES blocks needed for the low voltage differential signaling standard (LVDS).
Another challenge for implementing the soft solution on an FPGA relates to achieving the necessary maximum clock frequency. For example, in Cyclone II FPGAs, the LVDS receiver is targeted at 805 Mbps, but the on-chip clock network maximum frequency is only 402.5 MHz. Soft DDIO blocks that use a double clocking method are implemented to overcome this problem. A double clocking method samples data on both the rising and the falling edges of the clock signal, effectively operating at half the LVDS data rate. In Stratix FPGAs that use a hard SERDES architecture, a dedicated hard LVDS clock network is implemented to achieve a maximum frequency running at the same frequency as the LVDS data rate.
Altera's low cost Cyclone FPGAs are able to support a LVDS system interface at a high operating frequency by implementing soft DDIO blocks. However, the receiver input skew margin is small in Cyclone FPGAs, because of the delay caused by the programmable logic elements and the programmable interconnect wires. The small receiver input skew margin is not practical for many board designs.
Each IO decoder in Cyclone FPGAs consists of only three IO registers (on a per port basis). The three IO registers are the data-in register, the data-out register, and the output enable register. In Stratix FPGAs, two additional registers are implemented to support hard DDIO blocks in the IO decoder. These two additional registers were removed in Cyclone FPGAs to save die area.
On Cyclone FPGAs, the edge triggered registers in programmable logic elements are used to build the soft DDIO input registers. In this implementation, the input data path from the IO pins travels from an LVDS input buffer through programmable interconnect wires to the edge triggered registers in programmable logic elements. The programmable interconnect wires and the edge driven registers that receive signals from one pair of differential IO pins are all in the same row or the same column of programmable logic elements.
The path through the programmable interconnect wires causes a larger sampling window and a reduced receiver input skew margin for the following reasons. The input data path is longer, because the programmable interconnect wires are relatively slow. The longer input data path causes a longer propagation delay and increases the setup time (TSU) used to determine the sampling window.
Due to the nature of the FPGA fitting process, not all LVDS channels can be guaranteed to have matched data paths. This causes mismatched propagation delays and widens up the sampling window.
Therefore, it would be desirable to provide techniques for implementing a low cost DDIO scheme that has reduced propagation delays, matched propagation delays between differential signals on multiple channels, and a minimal impact on die area.